Exams/review2015 count1k

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.

代码如下，就是在每个posedge加1，然后等待q == 999再恢复成0，代码如下：

module top_module ( input clk, input reset, output reg [9:0] q); always @(posedge clk) begin if (reset) begin // 同步复位，清零 q <= 10'd0; end else if (q == 10'd999) begin // 数到 999 后回 0 q <= 10'd0; end else begin // 否则正常累加 q <= q + 1'b1; end end endmodule

Exams/review2015 shiftcount

This is the first component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

首先构建一个移位寄存器，当shift_ena为1，q产生位移，而位移的最低进位可以变成q <= {q[2:0],data}，当count_ena为1的时候使用一个减法器，代码如下：

module top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always @ (posedge clk)begin if (shift_ena == 1)begin q <= {q[2:0],data}; end else if (count_ena ==1) begin q <= q - 1'b1; end else begin q <= q; end end endmodule

Exams/review2015 fsmseq

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

这就是一个序列检测器，使用四个状态，定义为A,B,C,D，状态定义分别如下：

A:reset初始状态，data =0 保持在A状态，data =1 转移到B状态

B:0回到A，1转移到C

C:0转移到D，1保持C

D:1转移到E，0回到A

E:保持E锁存

代码如下：

module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter [2:0] A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100; reg [2:0] state,nextstate; //transition always @(*)begin case(state) A:nextstate = data?B:A; B:nextstate = data?C:A; C:nextstate = data?C:D; D:nextstate = data?E:A; E:nextstate = E; default:nextstate = A; endcase end //flip-flop always @(posedge clk) begin if (reset) begin state <= A; end else begin state <= nextstate; end end //output assign start_shifting = (state == E); endmodule

Exams/review2015 fsmshift

This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset)

代码如下：

module top_module ( input clk, input reset, // Synchronous reset output shift_ena); reg [2:0] count; always @(posedge clk) begin if (reset) count <= 3'd0; else if (count < 3'd4) count <= count + 1'b1; end assign shift_ena = (count < 3'd4); endmodule

Exams/review2015 fsm

已经给出状态图，直接根据状态图来写就可以，代码如下：

module top_module ( input clk, input reset, // Synchronous reset input data, input done_counting, input ack, output shift_ena, output counting, output done ); // 状态定义 // 使用足够的状态来处理 1101 序列检测和移位计数 parameter S_RESET = 0, S_1 = 1, S_11 = 2, S_110 = 3, // 序列检测状态 S_SHIFT_1 = 4, S_SHIFT_2 = 5, S_SHIFT_3 = 6, S_SHIFT_4 = 7, // 移位 4 周期 S_COUNTING = 8, S_DONE = 9; reg [3:0] state, next_state; // 状态转移逻辑 always @(*) begin case (state) // --- 阶段 1: 序列检测 (1101) --- S_RESET: next_state = data ? S_1 : S_RESET; S_1: next_state = data ? S_11 : S_RESET; S_11: next_state = data ? S_11 : S_110; S_110: next_state = data ? S_SHIFT_1 : S_RESET; // --- 阶段 2: 移位使能 (持续 4 个周期) --- S_SHIFT_1: next_state = S_SHIFT_2; S_SHIFT_2: next_state = S_SHIFT_3; S_SHIFT_3: next_state = S_SHIFT_4; S_SHIFT_4: next_state = S_COUNTING; // --- 阶段 3: 等待计数器完成 --- S_COUNTING: next_state = done_counting ? S_DONE : S_COUNTING; // --- 阶段 4: 等待用户确认 --- S_DONE: next_state = ack ? S_RESET : S_DONE; default: next_state = S_RESET; endcase end // 状态寄存器 (同步复位) always @(posedge clk) begin if (reset) state <= S_RESET; else state <= next_state; end // 输出逻辑 assign shift_ena = (state == S_SHIFT_1 || state == S_SHIFT_2 || state == S_SHIFT_3 || state == S_SHIFT_4); assign counting = (state == S_COUNTING); assign done = (state == S_DONE); endmodule

Exams/review2015 fancytimer

我只能说gemini写的又快又好。

module top_module ( input clk, input reset, // 同步复位 input data, output [3:0] count, output counting, output done, input ack ); // 状态定义 parameter S_SEARCH = 0, S_1 = 1, S_11 = 2, S_110 = 3, S_SHIFT0 = 4, S_SHIFT1 = 5, S_SHIFT2 = 6, S_SHIFT3 = 7, S_COUNT = 8, S_DONE = 9; reg [3:0] state, next_state; reg [3:0] delay_regs; // 存储移入的 4 位延迟值 reg [9:0] fast_cnt; // 1000 进制计数器 (0-999) reg [3:0] slow_cnt; // 千位计数器 (对应 count 输出) // 1. 状态转移逻辑 always @(*) begin case (state) // 序列检测 1101 S_SEARCH: next_state = data ? S_1 : S_SEARCH; S_1: next_state = data ? S_11 : S_SEARCH; S_11: next_state = data ? S_11 : S_110; S_110: next_state = data ? S_SHIFT0 : S_SEARCH; // 移位 4 个周期 (S_SHIFT0 到 S_SHIFT3) S_SHIFT0: next_state = S_SHIFT1; S_SHIFT1: next_state = S_SHIFT2; S_SHIFT2: next_state = S_SHIFT3; S_SHIFT3: next_state = S_COUNT; // 计数阶段：当 slow_cnt 为 0 且 fast_cnt 数到 999 时结束 S_COUNT: next_state = (slow_cnt == 0 && fast_cnt == 999) ? S_DONE : S_COUNT; // 等待确认 S_DONE: next_state = ack ? S_SEARCH : S_DONE; default: next_state = S_SEARCH; endcase end // 2. 状态寄存器 always @(posedge clk) begin if (reset) state <= S_SEARCH; else state <= next_state; end // 3. 移位寄存器逻辑 (MSB First) always @(posedge clk) begin if (state == S_SHIFT0 || state == S_SHIFT1 || state == S_SHIFT2 || state == S_SHIFT3) begin delay_regs <= {delay_regs[2:0], data}; end end // 4. 计数器逻辑 always @(posedge clk) begin if (state == S_COUNT) begin if (fast_cnt == 10'd999) begin fast_cnt <= 10'd0; if (slow_cnt > 0) slow_cnt <= slow_cnt - 1'b1; end else begin fast_cnt <= fast_cnt + 1'b1; end end else if (next_state == S_COUNT && state == S_SHIFT3) begin // 在进入 COUNT 状态的前一刻，预载 delay 值 // 这里的 delay_regs 已经包含了刚刚移入的 4 位数据 fast_cnt <= 10'd0; slow_cnt <= {delay_regs[2:0], data}; end else begin fast_cnt <= 10'd0; end end // 5. 输出赋值 assign counting = (state == S_COUNT); assign done = (state == S_DONE); assign count = slow_cnt; endmodule

module top_module( input d, input done_counting, input ack, input [9:0] state, // 10-bit one-hot current state output B3_next, output S_next, output S1_next, output Count_next, output Wait_next, output done, output counting, output shift_ena ); // 状态索引参数 parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9; // --- 次态逻辑 (Next State Logic) --- // B3 的上一个状态是 B2 assign B3_next = state[B2]; // 回到 S 状态的情况： // 1. 在 S 状态输入 0 (state[S] & ~d) // 2. 在 S1 状态输入 0 (state[S1] & ~d) // 3. 在 S110 状态输入 0 (state[S110] & ~d) // 4. 在 Wait 状态收到确认 (state[Wait] & ack) assign S_next = (state[S] & ~d) | (state[S1] & ~d) | (state[S110] & ~d) | (state[Wait] & ack); // 进入 S1 的情况：在 S 状态输入 1 assign S1_next = state[S] & d; // 进入 Count 的情况： // 1. 从 B3 转移而来 // 2. 在 Count 状态且计数未完成 (~done_counting) assign Count_next = state[B3] | (state[Count] & ~done_counting); // 进入 Wait 的情况： // 1. 计数完成 (state[Count] & done_counting) // 2. 在 Wait 状态且没有收到 ack (~ack) assign Wait_next = (state[Count] & done_counting) | (state[Wait] & ~ack); // --- 输出逻辑 (Output Logic) --- // done 仅在 Wait 状态有效 assign done = state[Wait]; // counting 仅在 Count 状态有效 assign counting = state[Count]; // shift_ena 在 B0, B1, B2, B3 状态下有效 assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3]; endmodule

不知道为什么fsm serialdp那道题gemini一直写的不对。。。